Daho_Cro ako se ne varam, to je kao zadnji labos, za vhdl sam dobio sve bodove pa bi moglo bit okej. jedino nez zasto imamo zadane i adrese ako treba samo entity i arhitekturu
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity movavg4 is
port (
clk : in std_logic;
rst : in std_logic;
-- Adresna sabirnica
port_id : in std_logic_vector(7 downto 0);
-- Podatkovna sabirnica za pisanje u registar, spaja se na out_port od KCPSM6
in_port : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
-- Podatkovna sabirnica za Ä?itnaje iz registra, spaja se na in_port od KCPSM6
out_port : out std_logic_vector(7 downto 0);
read_strobe : in std_logic
) ;
end entity ;
architecture arch of movavg4 is -- Nadopunite opis arhitekture sklopa
signal x3 : std_logic_vector(9 downto 0) := "0000000000";
signal x2 : std_logic_vector(9 downto 0) := "0000000000";
signal x1 : std_logic_vector(9 downto 0) := "0000000000";
signal x0 : std_logic_vector(9 downto 0) := "0000000000";
signal result : std_logic_vector(9 downto 0) := "0000000000";
signal pun : std_logic_vector(2 downto 0) := "000";
begin
output : process (clk)
begin
if rising_edge(clk) then
if rst = '1' or (port_id = "00000010" and write_strobe = '1') then
x3 <= "0000000000";
x2 <= "0000000000";
x1 <= "0000000000";
x0 <= "0000000000";
result <= "0000000000";
out_port <= "00000000";
pun <= "000";
else
if write_strobe = '1' then
if pun /= "100" then --4 dekadski
pun <= pun + 1;
end if;
x3 <= x2;
x2 <= x1;
x1 <= x0;
x0 <= "00" & in_port;
end if;
if read_strobe = '1' then
out_port <= result(9 downto 2);
end if;
end if;
elsif falling_edge(clk) then
if pun = "100" then
result <= x0 + x1 + x2 + x3;
else
result <= "0000000000";
end if;
end if;
end process;
end architecture arch;
ako nesto ne valja vicite
